1. Field of the Invention
The present invention generally relates to a stacked chip assembly, and more specifically, to a stacked chip assembly wherein two chips are stacked together on a lead frame.
2. Description of the Related Art
In a LOC (Lead-on-Chip) device, a die pad of a lead frame is not used. Instead, an inner lead portion of a lead frame extends over and attaches to an active surface of a semiconductor chip to be packaged. Then bonding pads of the chip are electrically interconnected to the corresponding inner lead portion. The LOC packaging technology provides a useful method for increasing the packaging efficiency of conventional package devices. Conventional stack package devices employ a three dimensional stacking technology comprising at least two chips within a single package. The stacked package device is suitable for use in increasing memory capacity of DRAM (Dynamic Random Access Memory) package devices.
FIG. 1 is a cross sectional view of a conventional LOC type stacked chip assembly disclosed in U.S. Pat. No. 5,332,922 issued on Jul. 26, 1994 to Oguchi et. al. The stacked chip assembly mainly includes a first chip 101, a second chip 102, a first lead frame 103, and a second lead frame 104. The first chip 101 is disposed on the lower surface of the first lead frame 103 and is electrically interconnected thereto by bonding wires 105. The second chip 102 is disposed on the lower surface of the second lead frame 104 and is electrically interconnected thereto by bonding wires 106. Then, the second lead frame 104 is inverted and bonded to the first lead frame 103 wherein the corresponding leads thereof are bonded by using a YAG (Yttrium Aluminum Garnet) laser beam. Then, the stacked chip assembly is encapsulated in a resin package 107. However, in this conventional stacked chip assembly, the bonding wires 105 and 106 must be spaced apart enough to prevent electrical shorts therebetween, and the first lead frame 103 and the second lead frame 104 are disposed between the first chip 101 and the second chip 102. These both act as limitations in reducing the thickness of the stacked chip assembly. Because the first chip 101 and the second chip 102 must be electrically connected to the first lead frame 103 and the second lead frame 104 respectively, the assembly process becomes complicated. Moreover, because the inner leads of the first lead frame 103 and the second lead frame 104 are bonded by using a YAG laser beam, the stacked package devices are manufactured at a higher cost.
FIG. 2 is a cross sectional view of another conventional LOC type stacked chip assembly disclosed in U.S. Pat. No. 5,804,874 issued on Sep. 8, 1998 to An et. al. The stacked chip assembly mainly includes a first chip 201, a second chip 202, a first lead frame 203, and a second lead frame 204. The first chip 201 is disposed on the lower surface of the first lead frame 203 and is electrically interconnected thereto by bonding wires 205. The second chip 202 is disposed on the lower surface of the second lead frame 204 and is electrically interconnected thereto by bonding wires 206. The second lead frame 204 is bonded to the first lead frame 203 by a conductive adhesive tape 207 or by the YAG (Yttrium Aluminum Garnet) laser beam The second chip 202 is insulated from the first lead frame 203 by an insulating adhesive film 208. Then, the stacked chip assembly is encapsulated in a resin package 209.
However, in the conventional stacked chip assembly disclosed in U.S. Pat. No. 5,804,874, the corresponding leads of the first lead frame 103 and the second lead frame 104 must be accurately positioned for bonding together in order to prevent electrical shorts therebetween. This makes the stacked chip assembly difficult for manufacturing.
Comparing with the stacked chip assembly of U.S. Pat. No. 5,332,922, the stacked chip assembly of U.S. Pat. No. 5,804,874 has significantly reduced the thickness of the stacked package and the times for bending the leads of the lead frames, thereby simplifying the assembly process therefor. However, the thickness of this package device and the need of using different lead frames in shape for assembly process still fail to meet the future requirements for they semiconductor industry.
Accordingly, the present invention is intended to provide a stacked chip assembly which reduces the thickness thereof and is manufactured with more simplified assembly process.